1. Field of the Invention
The present invention relates to a high-speed and high-precision comparator circuit for comparing two small signals at a high speed and outputting a digital value according to a magnitude relation of these signals in a high-speed A/D capacitor or the like.
2. Description of the Related Art
As a comparator circuit used for an A/D capacitor or the like, one configured by an amplifier and a latch circuit for outputting a digital value in synchronization with a clock signal has been known. FIG. 1A shows an example of such a conventional comparator circuit. The comparator circuit shown in this drawing is configured by connecting a differential amplifier circuit having NMOS transistors M1, M2 and a current mirror load circuit composed of PMOS transistors M3, M4, M5, M6 to a latch circuit configured by two inversion amplifiers (invertors) that are connected so that an input of one amplifier is made into an output of other amplifier.
Two inversion amplifiers are configured by a NMOS transistor M7 and a PMOS transistor M11, and a NMOS transistor M8 and a PMOS transistor M12, respectively. In addition, the inversion amplifiers are provided with a NMOS transistor M9 for equalizing output signals OUTP and OUTN, and a transistor M10 for operating the inversion amplifiers in synchronization with a clock signal CLK.
In the differential amplifier circuit having the current mirror circuit, a source of the transistors M1 and M2 is connected to a power source 11, and two input signals INP and INN are applied to gates of the transistors M1 and M2, respectively. To drains of the transistors M1 and M2, drains and gates of the transistors M3 and M4, and gates of the transistors M5 and M6 are respectively connected. Sources of the transistors M3, M4, M5 and M6 are connected to a supply voltage VDD, respectively, and the drains of the transistors M5 and M6 are connected to the inputs and the outputs of the inversion amplifier (inverter).
In the latch circuit configured by two inversion amplifiers, a transistor M9 is connected between the output terminals OUTP and OUTN, and the clock signal CLK is applied to a gate of the transistor M9. When this clock signal CLK is at a High level, the transistor M9 turns the power on, and the output terminals OUTP and OUTN are equalized. At the same time, the clock signal CLK is applied to a gate of a transistor M10 to make the transistor M10 non-conductive. As a result, the latch circuit is made into a non-active status.
A source of the transistors M7 and M8 is connected to an earth potential, and a gate of the transistor M7 is connected to a drain of the transistor M8 and the output terminal OUTP. In addition, a gate of the transistor 8 is connected to a drain of the transistor M7 and the output terminal OUTN. A source of a transistor M10 is connected to the supply voltage VDD, and a drain thereof is connected to a source of transistors M11 and M12. Gates of transistors M11 and M12 are connected to the output terminals OUTP and OUTN, respectively; and drains thereof are connected to the output terminals OUTP and OUTN, respectively.
The operation of a conventional comparator circuit will be described below.
When the clock signal CLK is at the High level, if the transistor M9 turns the power on, the output terminals OUTP and OUTN are equalized to the equal potential. At the same time, two input signals INP and INN are applied to the gates of the transistors M1 and M2 since the transistor M10 is made into the non-conductive status, however, an input signal is not differentially amplified due to the differential amplifier circuit having the current mirror load circuit since the output terminals OUTP and OUTN are equalized to the equal potential.
Next, if the clock signal CLK transits to a Low level, the transistor M9 is made into a non-active status, a potential difference between the input signals INP and INN that are applied to the transistors M1 and M2 is slightly amplified in the differential amplifier circuit having the current mirror load circuit to be outputted to the output terminals OUTP and OUTN. At the same time, the transistor M10 is made into a conductive status, the latch circuit configured by two inversion amplifiers configured by the transistors M7 and M11, and the transistors M8 and M12 is operated (activated), the small potential difference between the output terminals OUTP and OUTN amplified by the differential amplifier circuit having the current mirror load circuit is rapidly enlarged and amplified to a degree of the supply voltage or the earth potential level, and this amplified voltage is held in the output terminals OUTP and OUTN (see FIG. 1B).
For example, this sort of comparator circuit is disclosed in JP-A-5-67950 and JP-A-202-23774.
In the above-described comparator circuit, the voltage levels of the output terminals OUTP and OUTN should be decided by the magnitude relation between the input signals INP and INN at a leading edge of the clock signal CLK, however, when the potential difference of the input signals INP and INN is small, the potential difference of the output terminals OUTP and OUTN is rapidly changed due to the amplification operation of the latch circuit, and this results in returning of the voltage change in the output terminals OUTP and OUTN to the side of the input signals INP and INN due to a parasitic capacitance (C1gd, C2gd, C5gd, C6gd) between the gate and the drain of the transistors M1, M5, and M2, M6. Therefore, this involves a problem such that a so-called kickback phenomenon, in which the voltage relation between the input signals INP and INN is inversed, occurs and then, a malfunction may occur.
In addition, wiring resistance and wiring capacitance from the drain of the transistor M5 to the drains of the transistors M8 and M12, and the gates of the transistors M7, M11 may be slightly different from those from the drain (or the source) of the transistor M9 and the drain of the transistor M6 to the drains of the transistors M7, M11 and the gates of the transistors M8, M12. Therefore, in the event of deciding the magnitude relation of the input signals INP and INN having the small voltage difference, a small difference is generated in the speed of the voltage level change of the output terminals OUTP and OUTN by the amplifier having the current mirror load. In the conventional comparator circuit shown in FIG. 1A, the amplification operation is started by the latch circuit at the same time as the amplification operation by the differential amplifier having the current mirror load, and this involves a problem such that, under the condition that the voltage level amplified by the differential amplifier having the current mirror load is not determined, a wrong voltage level is held if the voltage level is rapidly amplified.